{"id":149,"date":"2016-05-10T01:03:43","date_gmt":"2016-05-10T01:03:43","guid":{"rendered":"http:\/\/sites.nyuad.nyu.edu\/dfx\/?page_id=149"},"modified":"2020-11-12T11:12:36","modified_gmt":"2020-11-12T11:12:36","slug":"patents","status":"publish","type":"page","link":"https:\/\/sites.nyuad.nyu.edu\/dfx\/patents\/","title":{"rendered":"Patents"},"content":{"rendered":"

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  1. Ozgur Sinanoglu, \u201cSystem, Method, Computer-Accessible Medium, And Circuit For Logic Locking\u201d, U.S. Patent pending, filed May 2020<\/li>\n
  2. Ozgur Sinanoglu, Muhammad Yasin and Jeyavijayan Rajendran, \u201cSystem, Method and Computer-Accessible Medium for Stripped-Functionality Logic Locking\u201d, U.S. Patent pending, filed Oct 2017.<\/li>\n
  3. Ozgur Sinanoglu, Muhammad Yasin and Jeyavijayan Rajendran, \u201cSystem, Method and Computer-Accessible Medium for IC Camouflaging for Minterm Protection\u201d, U.S. Patent pending, accepted<\/strong> May 2020.<\/li>\n
  4. Ozgur Sinanoglu, Muhammad Yasin and Jeyavijayan Rajendran, \u201cSystem, Method and Computer-Accessible Medium for Satisfiability Resistant Attack Resistant Logic Locking\u201d, U.S. Patent pending, accepted<\/strong> Aug 2020.<\/li>\n
  5. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, \u201cSystem, Method And Computer-Accessible Medium For Fault Analysis Driven Selection Of Logic Gates To Be Camouflaged\u201d, U.S. Patent No. US10073728B2, issued<\/strong> Sep 11, 2018, published<\/strong> under International Publication No. WO 2015\/038587 by World Intellectual Property Organization.<\/li>\n
  6. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, \u201cSecurity-Centric Electronic System Design\u201d, U.S. Patent pending, filed Mar 2015.<\/li>\n
  7. Jeyavijayan Rajendran, Youngok Pino, Ramesh Karri and Ozgur Sinanoglu, \u201cSystem, Method and Computer-Accessible Medium for Facilitating Logic Encryption\u201d, U.S. Patent No. 9,817,980, issued<\/strong> Nov 14, 2017.<\/li>\n
  8. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri \u201cSystem, Method and Computer-Accessible Medium for Providing Secure Split Manufacturing\u201d, U.S. Patent pending, accepted<\/strong> Aug 30 2018, published<\/strong> under International Publication No. WO 2014\/153029 by World Intellectual Property Organization.<\/li>\n
  9. Ozgur Sinanoglu, \u201cTest Access System, Method and Computer Accessible Medium for Chips with Spare Identical Cores\u201d, U.S. Patent No. 9,262,292, issued<\/strong> Feb 2016.<\/li>\n
  10. Ozgur Sinanoglu, \u201cSystem, Method and Computer-Accessible Medium for DfT Support for Launch and Capture Power Reduction in Launch-Off-Capture Testing\u201d, U.S. Patent No 9,170,298, issued<\/strong> Oct 2015.<\/li>\n
  11. Ozgur Sinanoglu, \u201cSystems, Processes and Computer-Accessible Medium for Providing a Bidirectional Scan Path for Peak Capture Power Reduction in Launch-Off-Shift Testing\u201d, U.S. Patent pending, U.S. Patent No. 10,203,368, issued<\/strong> Feb 11, 2019.<\/li>\n
  12. Jeyavijayan Rajendran, Youngok Pino, Ramesh Karri and Ozgur Sinanoglu, \u201cSystems, Processes and Computer-Accessible Medium for Providing Logic Encryption Utilizing Fault Analysis\u201d, U.S. Patent No. 9,081,929, issued<\/strong> July 14, 2015.<\/li>\n
  13. Ozgur Sinanoglu, \u201cArchitecture, System, Method and Computer-Accessible Medium for Toggle-Based Masking\u201d, U.S. Patent No. 8,756,468, issued<\/strong> June 17, 2014.<\/li>\n
  14. Ozgur Sinanoglu, \u201cArchitecture, System, Method and Computer-Accessible Medium for Eliminating Scan Performance Penalty\u201d, U.S. Patent No. 8,726,109, issued<\/strong> May 13, 2014.<\/li>\n
  15. Ozgur Sinanoglu, \u201cArchitecture, System, Method and Computer-Accessible Medium for Partial Scan Testing\u201d, U.S. Patent No. 9,599,671, issued<\/strong> March 21, 2017.<\/li>\n
  16. Ozgur Sinanoglu, \u201cArchitecture, System, Method and Computer-Accessible Medium for Expedited-Compaction for Scan Power Reduction\u201d, U.S. Patent pending, accepted<\/strong> Oct 2018.<\/li>\n
  17. Vinayaka Jyothi, Jeyavijayan Rajendran, Ramesh Karri and Ozgur Sinanoglu, \u201cDesign and Analysis of Ring Oscillator Based Design-for-Trust Technique\u201d, U.S. Patent No. 9,081,991, issued<\/strong> July 15, 2015.<\/li>\n
  18. Ozgur Sinanoglu and Sobeeh Almukhaizim, \u201cCircuit and Method for Increasing Scan Cell Observability of Response Compactors\u201d, U.S. Patent No. 8,006,150, issued<\/strong> August 23, 2011.<\/li>\n
  19. Sobeeh Almukhaizim and Ozgur Sinanoglu, \u201cCircuit and Method Providing Dynamic Scan Chain Partitioning\u201d, U.S. Patent No. 7,937,634, issued<\/strong> May 6, 2011.<\/li>\n
  20. Ozgur Sinanoglu, \u201cCircuit for Boosting Encoding Capabilities of Test Stimulus Decompressors\u201d, U.S. Patent No. 7,930,607, issued<\/strong> Apr 19, 2011.<\/li>\n<\/ol>\n

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    Ozgur Sinanoglu, \u201cSystem, Method, Computer-Accessible Medium, And Circuit For Logic Locking\u201d, U.S. Patent pending, filed May 2020 Ozgur Sinanoglu, Muhammad Yasin and Jeyavijayan Rajendran, \u201cSystem, Method and Computer-Accessible Medium for Stripped-Functionality Logic Locking\u201d, U.S. Patent pending, filed Oct 2017. Ozgur Sinanoglu, Muhammad Yasin and Jeyavijayan Rajendran, \u201cSystem, Method and Computer-Accessible Medium for IC Camouflaging for […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","_exactmetrics_skip_tracking":false,"_exactmetrics_sitenote_active":false,"_exactmetrics_sitenote_note":"","_exactmetrics_sitenote_category":0,"footnotes":""},"class_list":["post-149","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/pages\/149","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/comments?post=149"}],"version-history":[{"count":10,"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/pages\/149\/revisions"}],"predecessor-version":[{"id":1118,"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/pages\/149\/revisions\/1118"}],"wp:attachment":[{"href":"https:\/\/sites.nyuad.nyu.edu\/dfx\/wp-json\/wp\/v2\/media?parent=149"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}