First Chip Resilient to Untrusted Fabrication and Reverse-Engineering

ARM Microprocessor inside

Secured via Stripped Functionality Logic Locking

“Provably Secure Logic Locking” at ACM Computer & Communications Security (CCS) `17

Design-for-Excellence Team

Mission of the DfX Lab:

We are a research team in NYU Abu Dhabi, whose main focus is the reliability and security of electronic chips. With the increasing complexity of designs, enhanced capabilities of engraving smaller transistors on silicon, and low-power, high-performance operation requirements, integrated circuits are becoming more and more vulnerable to reliability and security threats. Electronic chips manufactured today exhibit a higher defect rate, fail more often during their mission-mode operation, die quicker in the field, and thanks to globalization and outsourcing, are more prone to security threats such as counterfeiting, IP piracy and hardware trojans.

Our mission is to design these electronic chips with built-in defense mechanisms, in order to expose defective chips more easily and cost-effectively, make them resilient to errors during mission mode, expose any intentional malicious alteration of the chips and protect design IP from reverse engineering. We develop Design-for-Excellence techniques comprising of hardware design blocks and accompanying software CAD tools.

Prof. Ozgur Sinanoglu, Director

Ozgur SinanogluThe director of the DfX Lab is Prof. Ozgur Sinanoglu, who is an Associate Prof of ECE at New York University in Abu Dhabi. Prof. Ozgur Sinanoglu obtained his Ph.D. in Computer Science and Engineering from University of California, San Diego, in 2004. During his PhD, he was given the IBM PhD Fellowship Award in two consecutive years in 2001 and 2002, and his PhD thesis won the CSE PhD Dissertation Award in UCSD in 2005. Subsequently, he worked for Qualcomm in San Diego as a senior Design-for-Testability engineer, primarily responsible for developing cost-effective test solutions for low-power SOCs. He then joined New York University in Abu Dhabi in 2010. Upon spending his integration year as a visiting Faculty in New York at the ECE Department of NYU Tandon, he joined the Faculty in Abu Dhabi in 2011. His primary field of research is the reliability and security of integrated circuits, mostly focusing on CAD tool development. He has more than 160 conference and journal papers in addition to around 20 issued and pending patents. His research has been funded by US National Science Foundation, US Army Research Office (Department of Defense), Semiconductor Research Corporation, GlobalFoundries and Advanced Technology Investment Company.

He is currently serving as:

  • Program Chair for IEEE ICCD 2017
  • General Chair for ACM ASIACCS 2017
  • Program Co-chair for IEEE ICCD 2016
  • Technical Program Committee Member for ITC, DAC, DATE (track chair), VTS, ETS (track chair), VLSI-SOC (track co-chair), ACNS, DFTS, LATS, DTIS
  • Journal editorial board member for IEEE TIFS, JETTA, Elsevier MEJ, IET CDT
  • Guest Editor for IEEE TCAD (Special Issue on Hardware Security), ACM JETC (Special Issue on Hardware Security), IEEE TETC (Special Issue on Hardware Security), IEEE TETC (Special Issue on Emerging Technologies in Computer Design)

Contact:

  • Email: ozgursin at nyu dot edu
  • Tel: +971 262 84388

 

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Current News

Our research in The National

Our research is featured in an article titled “NYU Abu Dhabi Engineers seek to make cities more secure” in The National. Click for the National...

US Army Research Office (Department of Defense) provides $400K funding

US Army Research Office (Department of Defense) provides $400K funding for our research on IC camouflaging. The goal of the project is to develop layout level countermeasures against reverse engineering. The project will develop metrics to guide the insertion of...

US National Science Foundation provides $500K funding

US National Science Foundation provides $500K funding for our research on secure high-level synthesis. The goal of the project is to develop novel high-level synthesis methodologies that will produce reverse-engineering resilient designs. This a joint project with...