List of All Publications

Book

  1. Sinanoglu O., Rajendran J., and Yasin M. (2019) Trustworthy Hardware Design: Combinational Logic Locking Techniques. Springer, Cham.

Book Chapters

  1. Yasin, M., Mazumdar, B., Rajendran, J., Sinanoglu, O. (2018) Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution: Design and Implementation. In: Elfadel, A., Ismail, M. (eds) The IoT Physical Layer. Springer, Cham.
  2. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Physical Unclonable Functions and Intellectual Property Protection Techniques”, Springer, to appear 2016.
  3. Sk Subidh Ali, Samah Saeed, Ozgur Sinanoglu and Ramesh Karri, “New Scan-Based Attack Using Only the Test Mode Scan Attack and an Input Corruption”, Springer, ISBN 978-3-319-23799-2, 2015.

Journal Publications

  1. Shubram Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, and Akash Kumar, “Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits”, IEEE Transactions on Emerging Topics in Computing, to appear 2021
  2. Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, and Evangeline F.Y. Young, “Deep Learning Analysis for Split Manufactured Layouts with Routing Perturbation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2021.
  3. Heechun Park, Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Majid Ahadi Dolatsara, Mohammed Nabeel, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay, Johann Knechtel, and Sung Kyu Lim, “Design Flow for Active Interposer-Based 2.5D ICs and Study of RISC-V Architecture with Secure NoC”, IEEE Transactions on Components, Packaging and Manufacturing Technology, to appear 2021.
  4. Nimisha Limaye, Emmanouil Kaligeros, Nikolaos Karousos, Irene G. Karibali, and Ozgur Sinanoglu, “Thwarting All Logic Locking Attacks: Dishonest Oracle with Truly Random Logic Locking”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2021.
  5. Muhammed Nabeel, Mohammad Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, and Johann Knechtel, “2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets”, IEEE Transcations on Computers, to appear 2020.
  6. Johann Knechtel, Satwik Patnaik, Muhammed Nabeel, Mohammad Ashraf, Yogesh S. Chauhan, Jorg Henkel, Ozgur Sinanoglu, and Hussam Amrouch, “Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)”, IEEE Micro, to appear 2020.
  7. Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Shaloo Rakheja, Ramesh Karri, and Ozgur Sinanoglu, “Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices”, IEEE Transactions on Emerging Topics in Computing, to appear 2020.
  8. Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Shaloo Rakheja, and Ozgur Sinanoglu, “SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory”, IEEE Access, to appear 2020
  9. Satwik Patnaik, Mohammad Ashraf, Johann Knechtel, and Ozgur Sinanoglu, “Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2020. DOI: 10.1109/TCAD.2020.2981034
  10. Abhrajit Sengupta, Nimisha Limaye, Muhammed Nabeel, Mohammad Ashraf and Ozgur Sinanoglu, “Truly Stripping Functionality for Logic Locking: A Fault-based Perspective”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2020. DOI: 10.1109/TCAD.2020.2968898
  11. Lilas Salem Alrahis, Nimisha Limaye, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, and Ozgur Sinanoglu, “ScanSAT: Unlocking Static and Dynamic Scan Obfuscation”, IEEE Transactions on Emerging Topics in Computing, to appear 2019. DOI: 10.1109/TETC.2019.2940750
  12. Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, and Michael Zuzak, “Keynote: A Disquisition on Logic Locking”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2019. DOI: 10.1109/TCAD.2019.2944586
  13. Satwik Patnaik, Mohammad Ashraf, Ozgur Sinanoglu and Johann Knechtel, “A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects”, IEEE Transactions on Emerging Topics in Computing, to appear 2019. DOI: 10.1109/TETC.2019.2933572
  14. Johann Knechtel, Jacek Gosciniak, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu and Mahmoud Rasras, “Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators”, IEEE/OSA Journal of Lightwave Technology, vol. 37, no. 15, 2019.
  15. Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu and Shaloo Rakheja, “Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2019. DOI: 10.1109/TCAD.2019.2917856
  16. Fangfei Yang, Ming Tang and Ozgur Sinanoglu, “Stripped Functionality Logic Locking with Hamming Distance Based Restore Unit (SFLL-hd) — Unlocked”, IEEE Transactions on Information Forensics & Security, vol. 14, no. 10, 2019.
  17. Bodhisatwa Mazumdar, Muhammad Yasin, Abhrajit Sengupta and Ozgur Sinanoglu, “Logic Locking with Provable Security Against Power Analysis Attacks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, 2020.
  18. Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu and Shaloo Rakheja, “Spin-based reconfigurable logic for power- and area-efficient applications”, IEEE Design and Test, vol. 36, no. 3, 2019.
  19. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu and Jeyavijayan Rajendran, “Removal Attacks on Logic Locking and Camouflaging Techniques”, IEEE Transactions on Emerging Topics in Computing, to appear 2017.
  20. Muhammad Yasin, Ozgur Sinanoglu and Jeyavijayan Rajendran, “Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging”, IEEE Transactions on Information Forensics & Security, to appear 2017.
  21. Muhammad Yasin, Temesghen Tekeste, Hani Saleh, Baker Mohammad, Ozgur Sinanoglu and Mohammed Ismail, “Ultra-low Power, Secure IoT Platform for Predicting Cardiovascular Diseases”, IEEE Transactions on Circuits and Systems I: Regular Papers, to appear 2017.
  22. Johann Knechtel, Ozgur Sinanoglu, Ibrahim Elfadel, Jens Lienig, and Cliff C. N. Sze, “Large-Scale 3D Chips: Challenges and Solution for Design Automation, Testing, and Trustworthy Integration”, IPSJ Transactions System LSI Design Methodology, to appear 2017. <invited>
  23. Chandra K. H. Suresh, Sule Ozev and Ozgur Sinanoglu, “Adaptive Reduction of the Frequency Search for Multi-Vdd Digital Circuits Using Variation Sensitive Ring Oscillators”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2017.
  24. Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “A Comparative Security Analysis of Current and Emerging Technologies”, IEEE Micro (Sept/Oct Special Issue on Security), to appear 2016.
  25. Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities”, ACM Transactions on Design Automation of Electronic Systems, to appear 2016.
  26. Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, and Krishnendu Chakrabarty, “Supply-Chain Security of Digital Microfluidic Biochips”, IEEE Computer Magazine, to appear 2016.
  27. Bodhisatwa Mazumdar, Samah Saeed, Sk Subidh Ali and Ozgur Sinanoglu, “Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers”, IEEE Transactions on Emerging Topics in Computing (TETC), to appear 2016.
  28. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Building Trustworthy Hardware Using Untrusted Components During High-Level Synthesis”, IEEE Transactions on Very Large Scale Integration Systems, to appear 2016.
  29. Samah Saeed and Ozgur Sinanoglu, “A Comprehensive Design-for-Test Infrastructure In the Context Of Security-Critical Applications”, IEEE Design and Test, to appear 2016.
  30. Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty and Ramesh Karri, “Security Assessment of Cyberphysical Digital Microfluidic Biochips”, IEEE/ACM Transactions on Computational Biology and Bioinformatics, to appear 2016 (DOI: 10.1109/TCBB.2015.2509991).
  31. Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “On Improving the Security of Logic Locking”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear 2016 (DOI: 10.1109/TCAD.2015.2511144).
  32. Chandra K. H. Suresh, Ozgur Sinanoglu and Sule Ozev, “Adapting to Varying Distributions of Unknown Response Bits”, ACM Transactions on Design Automation of Electronic Systems, to appear 2016.
  33. Chandra K. H. Suresh, Sule Ozev and Ozgur Sinanoglu, “Adaptive Generation of Unique IDs for Digital Chips Through Analog Excitation”, ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 3, pp. 46:1-46:18, 2015.
  34. Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu and Ramesh Karri, “Modeling, Detection, and Diagnosis of Faults in Multi-level Memristor Memories”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 822-834, 2015.
  35. Naghmeh Karimi, Arun Kanuparthi, Xueyang Wang, Ramesh Karri and Ozgur Sinanoglu, “MAGIC: Malicious Aging in Circuits/Cores”, ACM Transactions on Architecture and Code Optimization, vol. 12, no. 1, pp. 5:1-5:25, 2015.
  36. Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu and Ramesh Karri, “Belling the CAD: Towards Security-Centric Electronic System Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 11, pp. 1756-1769, 2015.
  37. Sk Subidh Ali, Samah Saeed, Ozgur Sinanoglu and Ramesh Karri, “Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 808-821, 2015.
  38. Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu and Ramesh Karri, “Security Vulnerability of Emerging Non-volatile Main Memories and Countermeasures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 1, pp. 2-15, 2015.
  39. Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett Rose, Youngok Pino, Ozgur Sinanoglu and Ramesh Karri, “Fault Analysis-based Logic Encryption”, IEEE Transactions on Computers, vol. 64, no. 2, pp. 410-425, 2015
  40. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Regaining Trust in VLSI Manufacturing: Design-for-Trust Techniques”, Proceedings of the IEEE, vol. 102, no. 8, pp. 1266-1282, 2014.
  41. Samah Saeed and Ozgur Sinanoglu, “DfT Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing”, IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 3, pp. 516-521, 2014.
  42. Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri and Ozgur Sinanoglu, “Sneak Path Testing of Crossbar-based Non-volatile Random Access Memories”, IEEE Transactions on Nanotechnology, vol. 12, no. 3, pp. 413-426, 2013.
  43. Ozgur Sinanoglu and Vishwani Agrawal, “Eliminating The Timing Penalty of Scan”, Journal of Electronic Testing: Theory and Applications, vol. 29, no. 1, pp. 103-114, February 2013.
  44. Abishek Ramdas and Ozgur Sinanoglu, “Testing Chips With Spare Identical Cores”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 7, pp. 1124-1135, 2013.
  45. Sobeeh Almukhaizim, Sara Bunian, and Ozgur Sinanoglu, “Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints”, Journal of Electronic Testing: Theory and Applications, vol. 29, no. 1, pp. 73-86, February 2013.
  46. Ozgur Sinanoglu, “Scan to Non-Scan Conversion Via Test Cube Analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, issue 2, pp. 289-300 2013.
  47. Samah Saeed, Ozgur Sinanoglu, and Sobeeh Almukhaizim, “Predictive Techniques for Projecting Test Data Compression”, IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 9, pp. 1762-1766, 2013.
  48. Samah Saeed and Ozgur Sinanoglu, “Expedited-Compact Architecture for Average Scan Power Reduction”, IEEE Design and Test of Computers, vol. 30, issue 3, pp. 25-33, 2013.
  49. Ozgur Sinanoglu, “Fault Model Independent, Maximal Compaction of Test Responses In the Presence of Unknown Response Bits”, The Computer Journal, vol. 55, no. 12, pp. 1525-1537, 2012.
  50. Samah Saeed and Ozgur Sinanoglu, “Multi-Modal Response Compaction Adaptive to X-Density Variation”, IET Computer and Digital Techniques, vol. 2, issue 6, pp. 69-77, 2012.
  51. Mehmet Hakan Karaata, Ozgur Sinanoglu, and Bader AlBdaiwi, “An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks”, The Computer Journal, vol. 55, no. 5, pp. 578-589, 2012.
  52. Ozgur Sinanoglu and Sobeeh Almukhaizim, “Unified 2-D X-Alignment for Improving the Observability of Response Compactors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, issue 11, pp. 1744-1757, 2011.
  53. Sobeeh Almukhaizim, Eman AlQuraishi and Ozgur Sinanoglu, “Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits”, Journal of Low Power Electronics, vol. 7, no. 4, pp. 1-12, October 2011.
  54. Nader Al-Awadhi, Ozgur Sinanoglu and Mohammed Al-Mulla, “Enhancing Enhancing Capacity of Combinational Test Stimulus Decompressors”, Journal of Science China, vol. 54, no. 8, pp. 1618-1634, 2011.
  55. Sobeeh Almukhaizim and Ozgur Sinanoglu, “A Novel Hazard-Free Majority Voter for NMR-Based Fault Tolerance in Asynchronous Circuits”, IET Computer and Digital Techniques, vol. 5, no. 4, pp. 306-315, 2011.
  56. Sobeeh Almukhaizim, Shouq Alsubaihi and Ozgur Sinanoglu, “On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power”, Journal of Electronic Testing: Theory and Applications, vol. 26, no. 4, pp. 465-481, 2010.
  57. Ozgur Sinanoglu, Mehmet Hakan Karaata and Bader AlBdaiwi, “An Inherently Stabilizing Algorithm for Node-To-Node Routing Over All Shortest Node-Disjoint Paths in Hypercube Networks”, IEEE Transactions on Computers, vol. 59, no. 7, pp. 995-999, 2010.
  58. Mohammed Al-Mulla, Ozgur Sinanoglu, Mohammed Taha and Nader Alawadhi, “Align-Encode Delay Assignment In The Case of XOR-Decompressors: Impact of Parallel Computations”, Journal of Interconnection Networks, vol. 10, no. 4, pp. 261-281, 2009.
  59. Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald and Jeff Rearick, “Test Data Volume Comparison: Monolithic vs Modular SOC Testing”, IEEE Design and Test of Computers, May/June, vol. 26, issue 3, pp. 25-37, 2009.
  60. Ozgur Sinanoglu, Mohammed Al-Mulla, Noora Shunaiber, and Alex Orailoglu, “Scan Cell Positioning for Boosting the Compression of Fan-out Networks”, Journal of Computer Science and Technology, vol. 24, no. 5, pp. 939-948, 2009.
  61. Mohammed Al-Mulla and Ozgur Sinanoglu, “A Distributed Algorithm for XOR-Decompression with Stimulus Fragment Move to Reduce Chip Testing Costs”, International Journal of Mathematical Models and Methods in Applied Sciences (Naun), vol. 3, no. 3, pp. 256-265, 2009.
  62. Ozgur Sinanoglu and Alex Orailoglu, “Application of Serial Transformations in Scan-Based SOC Test for Test Cost Reduction”, Kuwait Journal of Science and Engineering, vol. 36, no. 1B, pp. 167-195, 2009.
  63. Ozgur Sinanoglu, Mohammed Al-Mulla, and Mohammed Taha, “Utilisation of Inverse Compatibility For Test Cost Reductions”, IET Computer and Digital Techniques, vol. 3, no. 2, pp. 195-204, 2009.
  64. Ozgur Sinanoglu and Sobeeh Almukhaizim, “X-align: Improving the Scan Cell Observability of Response Compactors”, IEEE Transactions on Very Large Scale Integration Systems, vol. 17, issue 10, pp. 1392-1404, 2009.
  65. Ozgur Sinanoglu and Philip Schremmer, “Scan Chain Hold-Time Violations: Can They Be Tolerated?”, IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 6, pp. 815-826, 2009.
  66. Sobeeh Almukhaizim and Ozgur Sinanoglu, “Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 2, pp. 298-302, 2009.
  67. Ozgur Sinanoglu, “Scan Architecture with Align-Encode”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 12, pp. 2304-2317, 2008.
  68. Ozgur Sinanoglu and Tsvetomir Petrov, “Isolation Techniques for Soft Cores”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1453-1466, 2008.
  69. Ozgur Sinanoglu, “Improving the Effectiveness of Combinational Decompressors through Judicious Partitioning of Scan Cells”, Journal of Electronic Testing: Theory and Applications, 2008, vol. 24, no. 5, pp. 439-448, 2008.
  70. Ozgur Sinanoglu, “Construction of an Adaptive Scan Network for Test Time and Data Volume Reduction”, IET Computer and Digital Techniques, vol. 2, issue 1, pp. 12-22, 2008.
  71. Ozgur Sinanoglu, “Scan-In and Scan-Out Transition Co-optimization Through Modelling Generalized Serial Transformations”, Journal of Electronic Testing: Theory and Applications, vol. 24, no. 4, pp. 335-351, 2008.
  72. Kalim Qureshi, Paul Manuel and Ozgur Sinanoglu, “The Intertwinement of Pre-Task Assignment with Decentralized Resource Management Strategy for Heterogeneous Distributed Systems”, International Journal of Mathematics and Computer Science, vol. 2, no. 3, pp. 269-284, 2007.
  73. Ozgur Sinanoglu, “Low Cost Scan Test by Test Correlation Utilization”, Journal of Computer Science and Technology, vol. 22, no. 5, pp. 681-694, 2007.
  74. Ozgur Sinanoglu and Alex Orailoglu, “Test Power Reductions through Computationally Efficient Decoupled Scan Chain Modifications”, IEEE Transactions on Reliability, vol. 54, no. 2, pp. 215-223, 2005.
  75. Ozgur Sinanoglu and Alex Orailoglu, “Efficient RT-level Diagnosis”, Journal of Computer Science and Technology, vol. 20, no. 2, pp. 166-174, 2005.
  76. Ozgur Sinanoglu and Alex Orailoglu, “Fast and Energy-Frugal Deterministic Test Through Efficient Compression and Compaction Techniques”, Journal of Systems Architecture, vol. 50, no. 5, pp. 257-266, 2004.
  77. Ozgur Sinanoglu and Alex Orailoglu, “Compacting Test Buses for Deeply Embedded SOC Cores”, IEEE Design and Test of Computers, vol. 20, no. 4, pp. 22-29, 2003.
  78. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, “Reducing Average and Peak Test Power Through Scan Chain Modification”, Journal of Electronic Testing: Theory and Applications, vol. 19, no. 4, pp. 457-467, 2003.
  79. Ozgur Sinanoglu and Alex Orailoglu, “Efficient Construction of Aliasing-Free Compaction Circuitry”, IEEE Micro, vol. 22, no. 5, pp. 82-92, 2002.

Conference Proceedings/Presentations

IP: Interactive presentation with 4 pages of publication | POS: Poster presentation with 1-2 page(s) of publication | PrOnly: Presentation only; no publication

  1. Nimisha Limaye, Satwik Patnaik, and Ozgur Sinanoglu, “Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques”, IEEE/ACM Design Automation Test in Europe Conference (DATE), 2021.
  2. Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton and Samuel Pagliarini, “Design Obfuscation versus Test”, IEEE European Test Symposium (ETS), Talinn, Estonia, 2020.
  3. Nimisha Limaye and Ozgur Sinanoglu, “DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Grenoble, France, 2020.
  4. Julian Leonhard, Marie-Minerve Louerat, Hassan Aboushady, Ozgur Sinanoglu and Haralampos-G. Stratigopoulos, “Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application”, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 2019.
  5. Nimisha Limaye, Abhrajit Sengupta, Mohammad Nabeel, and Ozgur Sinanoglu, “Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access”, IEEE International Conference on Computer Aided Design (ICCAD), Westminster CO, US, 2019.
  6. Nimisha Limaye, Muhammad Yasin, and Ozgur Sinanoglu, “Revisiting Logic Locking for Reversible Computing”, IEEE European Test Symposium (ETS), Baden Baden, Germany, 2019.
  7. Alabi Bojesomo, Ibrahim Elfadel, and Ozgur Sinanoglu, “Piezo-PUF: Physical Unclonable Functions for Vacuum-Packaged, Piezoelectric MEMS”, IEEE Symposium on Design, Test, Fabrication, and Packaging of MEMS/MOEMS (DTIP), Paris, France, 2019.
  8. Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Hao Geng, Bei Yu, Ozgur Sinanoglu, Johann Knechtel, and Young Fung Yu, “Attacking Split Manufacturing From A Deep Learning Perspective”, IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV, US, 2019.
  9. Johann Knechtel, Satwik Patnaik and Ozgur Sinanoglu, “Protect Your Chip Design Intellectual Property: An Overview”, International Conference on Omni-Layer Intelligent Systems, Crete, Greece, 2019.
  10. Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Nabeel, Marie-Minerve Louerat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu and Haralampos-G. Stratigopoulos, “MixLock: Securing Mixed-Signal Circuits via Logic Locking”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Florence, Italy, 2019.
  11. Abhrajit Sengupta, Mohammad Nabeel, Johann Knechtel, and Ozgur Sinanoglu, “A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Florence, Italy, 2019.
  12. Lilas Salem Alrahis, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, and Ozgur Sinanoglu, “ScanSAT: Unlocking Obfuscated Scan Chains”, IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, 2019.
  13. Abhrajit Sengupta, Mohammad Nabeel, Mohammad Ashraf, and Ozgur Sinanoglu, “Customized Locking of IP blocks on a Multi-million-gate SoC”, IEEE International Conference on Computer Aided Design (ICCAD), San Diego CA, US, 2018.
  14. Satwik Patnaik, Mohammad Ashraf, Johann Knechtel, and Ozgur Sinanoglu, “Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security Driven CAD Flow for 3D ICs”, IEEE International Conference on Computer Aided Design (ICCAD), San Diego CA, US, 2018.
  15. Satwik Patnaik, Mohammad Ashraf, Johann Knechtel, and Ozgur Sinanoglu, “Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL”, IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, US, 2018.
  16. Abhrajit Sengupta, Mohammad Nabeel, Muhammad Yasin, and Ozgur Sinanoglu, “ATPG-Based Cost-Effective, Secure Logic Locking”, IEEE VLSI Test Symposium (VTS), San Francisco, CA, US, 2018.
  17. Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, and Shaloo Rakheja “Advancing Hardware Securiy Using Polymprphic and Stochastic Spin-Hall Effect Devices”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Dresden, Germany, 2018.
  18. Monir Zaman, Abhrajit Sengupta, Danxing Liu, Ozgur Sinanoglu, Yiorgos Makris, and Jeyavijayan Rajendran, “Towards Provably-Secure Performance Locking”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Dresden, Germany, 2018.
  19. Satwik Patnaik, Mohammad Ashraf, Johann Knechtel, and Ozgur Sinanoglu, “ConcertedWire Lifting: Enabling Secure and Cost-Effective Split Manufacturing”, IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Jeju Island, Korea, 2018.
  20. Muhammad Yasin, Abhrajit Sengupta, Mohammad Nabeel, Mohammad Ashraf, Jeyavijayan Rajendran, and Ozgur Sinanoglu, “Provably Secure Logic Locking: From Theory to Practice”, ACM Conference on Computer and Communications Security (CCS), Dallas TX, US, 2017.
  21.  Muhammad Yasin, Jeyavijayan Rajendran, and Ozgur Sinanoglu, “Evolution of Logic Locking”, IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Abu Dhabi, UAE, 2017.
  22. Satwik Patnaik, Mohammad Ashraf, Johann Knechtel, and Ozgur Sinanoglu, “Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging”, IEEE International Conference on Computer Aided Design (ICCAD), Irvine CA, US, 2017.
  23. Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammad Ashraf, Siddharth Garg, and Ozgur Sinanoglu, “Rethinking Split Manufacturing: An Information-Theoretic Approach With Secure Layout Techniques”, IEEE International Conference on Computer Aided Design (ICCAD), Irvine CA, US, 2017.
  24. Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrion Schaefer, Yiorgos Makris, Ozgur Sinanoglu, and Jeyavijayan Rajendran, “What to Lock? Functional and Parametric Locking”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, 2017.
  25. Johann Knechtel and Ozgur Sinanoglu, “On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity”, IEEE/ACM Design Automation Conference (DAC), Austin, TX, USA, 2017.
  26. Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan Rajendran and Ozgur Sinanoglu, “TTLock: Tenacious and Traceless Logic Locking”, IEEE Hardware Oriented Security and Trust Conference (HOST), Washington DC, US, 2017. POS
  27. Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan Rajendran and Ozgur Sinanoglu, “Security Analysis of Anti-SAT”, IEEE/ACM Asia South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, 2017.
  28. Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty and Ramesh Karri, “Microfluidic Encryption of on-Chip Biochemical Assays”, IEEE Biomedical Circuits & Systems Conference, Shanghai, China, 2016.
  29. Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan Rajendran and Ozgur Sinanoglu, “CamoPerturb: Secure IC Camouflaging for Minterm Protection”, IEEE International Conference on Computer Aided Design (ICCAD), Austin TX, US, 2016.
  30. Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “Power-Side-Channel Analysis of Carbon Nanotube FET Based Design”, IEEE International On-Line Testing Symposium (IOLTS), Sant Feliu de Guixos, Spain, 2016. POS
  31. Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan Rajendran and Ozgur Sinanoglu, “SARLock: SAT Attack Resistant Logic Locking”, IEEE Hardware Oriented Security and Trust Conference (HOST), Washington DC, US, 2016.
  32. Samah Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “Thwarting Timing Attacks on NEMS Relay Based Designs” IEEE VLSI Test Symposium (VTS), Las Vegas, NV, USA, 2016.
  33. Muhammad Yasin and Ozgur Sinanoglu, “Transforming Between Logic Locking and IC Camouflaging”, IEEE International Design and Test Symposium (IDT), Dead Sea, Jordan, 2015.
  34. Muhammad Yasin, Samah Saeed, Jeyavijayan Rajendran and Ozgur Sinanoglu, “Activation of Logic Encrypted Chips: Pre-Test or Post-Test?”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Dresden, Germany, 2016.
  35. Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty and Ramesh Karri, “Can Assay Outcomes of Digital Microfluidic Biochips be Manipulated?”, IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 2015.
  36. Muhammad Yasin, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “Security Analysis of Logic Encryption Against the Most Effective Side-Channel Attack: DPA”, IEEE International Symposium on Defect and Fault Tolerance (DFTS), Amherst, MA, USA, 2015.
  37. Sk Subidh Ali and Ozgur Sinanoglu, “Scan Attack on Elliptic Curve Cryptosystem”, IEEE International Symposium on Defect and Fault Tolerance (DFTS), Amherst, MA, USA, 2015.
  38. Samah Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “Timing Attack on NEMS Relay Based Design of AES”, IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Daejeon, South Korea, 2015.
  39. Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu, “Power Analysis Attacks on ARX: An Application to Salsa20”, IEEE International On-Line Testing Symposium (IOLTS), Halkidiki, Greece, 2015.
  40. Sk Subidh Ali and Ozgur Sinanoglu, “TMO: A New Class of Attack on Cipher Misusing Test Infrastructure”, IEEE VLSI Test Symposium (VTS), Napa, CA, USA, 2015.
  41. Jerry Backer, Ramesh Karri, Sk Subidh Ali, Ozgur Sinanoglu and David Hely “A Secure Design-for-Test Architecture to Thwart Attacks Throughout The Life Cycle of SoCs”, IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015.
  42. Sk Subidh Ali, Ozgur Sinanoglu and Ramesh Karri, “AES Design Space Exploration New Line for Scan Attack Resiliency”, IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Playa Del Carmen, Mexico, 2014.
  43. Samah Saeed and Ozgur Sinanoglu, “DfST: Design for Secure Testability”, IEEE International Test Conference (ITC), Seattle, WA, US, 2014.
  44. Samah Saeed, Sk Subidh Ali, Ozgur Sinanoglu and Ramesh Karri, “Test-Mode-Only Scan Attack and Countermeasure for Contemporary Scan Architectures”, IEEE International Test Conference (ITC), Seattle, WA, US, 2014.
  45. Sk Subidh Ali, Samah Saeed, Ozgur Sinanoglu and Ramesh Karri, “New Scan Attacks Against State-of-the-art Countermeasures and DFT”, IEEE Hardware Oriented Security and Trust Conference (HOST), Washington DC, US, 2014.
  46. Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri and Ozgur Sinanoglu, “Secure Memristor-Based Main Memory”, IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, 2014.
  47. Sk Subidh Ali, Ozgur Sinanoglu and Ramesh Karri, “Test-Mode-Only Scan Attack Using the Boundary Scan Chain”, IEEE European Test Symposium (ETS), Paderborn, Germany, 2014.
  48. Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri and Ozgur Sinanoglu, “Detection, Diagnosis, and Repair of Faults in Memristor-based Memories”, IEEE VLSI Test Symposium (VTS), Napa, CA, USA, 2014.
  49. Doohwang Chang, Sule Ozev, Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Dresden, Germany, 2014. IP
  50. Sachhidh Kannan, Ramesh Karri and Ozgur Sinanoglu, “Sneak path Testing and Fault Modeling for Multi-level Memristor-based Memories”, IEEE International Conference on Computer Design (ICCD), Ashville, NC, USA, 2013.
  51. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Security Analysis of Integrated Circuit Camouflaging”, ACM Conference on Computer and Communications Security (CCS), Berlin, Germany, 2013.
  52. Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “VLSI Testing based Security Metric for IC Camouflaging”, IEEE International Test Conference (ITC), Anaheim, CA, US, 2013.
  53. Sk Subidh Ali, Samah Saeed, Ozgur Sinanoglu and Ramesh Karri, “New Scan-Based Attack Using Only the Test Mode”, IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Istanbul, Turkey, 2013.
  54. Sk Subidh Ali, Samah Saeed, Ozgur Sinanoglu and Ramesh Karri, “Scan Attack in the Presence of Mode-Reset Countermeasure”, IEEE International On-Line Testing Symposium (IOLTS), Crete, Greece, 2013.
  55. Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu and Ramesh Karri, “High-level Synthesis for Security and Trust”, IEEE International On-Line Testing Symposium (IOLTS), Crete, Greece, 2013.
  56. Ozgur Sinanoglu, Yiorgos Makris and Ramesh Karri “Reconciling the Dichotomy Between Test and Security”, IEEE European Test Symposium (ETS), Avignon, France, 2013.
  57. Ozgur Sinanoglu, “Regaining Hardware Security and Trust”, IEEE Latin American Test Workshop (LATW), Cordoba, Argentina, 2013.
  58. Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri, “Is Split Manufacturing Secure?”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Grenoble, France, 2013.
  59. Chandra K. H. Suresh, Ender Yilmaz, Ozgur Sinanoglu and Sule Ozev, “Adaptive Reduction of The Frequency Search Space for Multi-Vdd Digital Circuits”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Grenoble, France, 2013. IP
  60. Sachhidh Kannan, Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Sneak Paths Testing of Memristor-based Memories”, International Conference on VLSI Design (VLSID), Pune, India, 2013.
  61. Ozgur Sinanoglu, “Leveraging Testing Tools for Protecting Design IP”, IEEE International Test Conference (ITC), Anaheim, CA, USA, Elevator Talks Session, 2012. PrOnly
  62. Sachhidh Kannan, Jeyavijayan Rajendran, Ozgur Sinanoglu and Ramesh Karri, “Engineering Crossbar based Emerging Memory Technologies”, IEEE International Conference on Computer Design (ICCD), Montreal, Canada, 2012. POS
  63. Ozgur Sinanoglu, “Test Access Mechanism for Chips with Spare Identical Cores”, IEEE International On-Line Testing Symposium (IOLTS), Sitges, Spain, 2012.
  64. Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu and Peter Maxwell, “Adaptive Testing: Conquering Process Variations”, IEEE European Test Symposium (ETS), Annecy, France, 2012.
  65. Abishek Ramdas and Ozgur Sinanoglu, “Toggle-Masking Scheme For X-Filtering”, IEEE European Test Symposium (ETS), Annecy, France, 2012.
  66. Chandra K. H. Suresh, Ozgur Sinanoglu and Sule Ozev, “Adaptive Testing of Chips With Varying Distributions of Unknown Response Bits”, IEEE European Test Symposium (ETS), Annecy, France, 2012.
  67. Samah Saeed and Ozgur Sinanoglu, “DfT Support for Launch and Capture Power Reduction in Launch-Off-Capture Testing”, IEEE European Test Symposium (ETS), Annecy, France, 2012.
  68. Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu and Ramesh Karri, “Security Analysis for Logic Obfuscation”, ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, US, 2012.
  69. Ozgur Sinanoglu and Vishwani Agrawal, “Retiming Scan Circuit to Eliminate Timing Penalty”, IEEE Latin American Test Workshop (LATW), Quito, Equador, 2012.
  70. Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu and Ramesh Karri, “Applying IC Testing Concepts To Secure ICs”, Government MicroCircuit Applications & Critical Technology Conference (GOMATECH), Las Vegas, NV, USA, Paper 23.3, 2012. PrOnly
  71. Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri and Youngok Pino, “Logic Encryption: A Fault Analysis Perspective”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Dresden, Germany, 2012.
  72. Ozgur Sinanoglu, “Eliminating Performance Penalty of Scan”, International Conference on VLSI Design (VLSID), New Delhi, India, 2012.
  73. Ozgur Sinanoglu, “Eliminating Performance Penalty of Scan”, IEEE International Test Conference (ITC), Anaheim, CA, USA, Elevator Talks Session, 2011. PrOnly
  74. Ozgur Sinanoglu, “Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing”, IEEE Asian Test Symposium (ATS), New Delhi, India, 2011.
  75. Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri and Youngok Pino, “Towards Securing Integrated Circuits”, ACM SiGDA University Booth at IEEE/ACM Design Automation Conference (DAC), 2011. PrOnly
  76. Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu and Ramesh Karri, “Design and Analysis of Ring Oscillator Based Design-for-Trust Technique”, IEEE North Atlantic Test Workshop (NATW), Lowell, MA, USA, 2011. PrOnly
  77. Ozgur Sinanoglu, “Toggle-based Masking Scheme for Clustered Unknown Response Bits”, IEEE European Test Symposium (ETS), Trondheim, Norway, 2011.
  78. Sobeeh Almukhaizim and Ozgur Sinanoglu, “Error-Resilient Design of Branch Predictors for Effective Yield Improvement”, IEEE Latin American Test Workshop (LATW), Porto de Galinhas, Brazil, 2011.
  79. Eman Alquraishi, Sobeeh Almukhaizim and Ozgur Sinanoglu, “Test Power Reduction Via Alignment of Stimulus and Response Bits”, IEEE Latin American Test Workshop (LATW), Porto de Galinhas, Brazil, 2011.
  80. Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu and Ramesh Karri, “Design and Analysis of Ring Oscillator Based Design-for-Trust Technique”, IEEE VLSI Test Symposium (VTS), Dana Point, CA, USA, 2011.
  81. Nader Alawadhi and Ozgur Sinanoglu, “Revival of Partial Scan: Test Cube Analysis Driven Conversion of Flip-Flops”, IEEE VLSI Test Symposium (VTS), Dana Point, CA, USA, 2011.
  82. Samah Saeed and Ozgur Sinanoglu, “Expedited Response Compaction for Scan Power Reduction”, IEEE VLSI Test Symposium (VTS), Dana Point, CA, USA, 2011.
  83. Sobeeh Almukhaizim, Sara Bunian and Ozgur Sinanoglu, “Reconfigurable Low-Power Concurrent Error Detection in Logic Circuits”, IEEE International Design & Test Workshop (D&T), Abu Dhabi, UAE, pp. 91-96, 2010.
  84. Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu and Sobeeh Almukhaizim, “Identification of IR-Drop Hot-Spots in Defective Power Distribution Network Using TDF ATPG”, IEEE International Design & Test Workshop (D&T), Abu Dhabi, UAE, pp. 122-127, 2010.
  85. Ozgur Sinanoglu, “Financial Implications of Security in VLSI Test”, Workshop on Information Security and Privacy, Abu Dhabi, UAE, 2010. PrOnly
  86. Nader Al-Awadhi, Ozgur Sinanoglu and Mohammed Al-Mulla, “Pattern Encodability Enhancements for Test Stimulus Decompressors”, IEEE Asian Test Symposium (ATS), Shanghai, China, pp. 173-178, 2010.
  87. Samah Saeed and Ozgur Sinanoglu, “XOR-Based Response Compactor Adaptive to X-Density Variation”, IEEE Asian Test Symposium (ATS), Shanghai, China, pp. 212-217, 2010.
  88. Ozgur Sinanoglu and Sobeeh Almukhaizim, “Predictive Analysis for Projecting Test Compression Levels”, IEEE International Test Conference (ITC), Austin, TX, USA, paper 9.3, 2010.
  89. Sobeeh Almukhaizim, Sara Bunian and Ozgur Sinanoglu, “Reconfigurable Low-Power Concurrent Error Detection in Logic Circuits”, IEEE International On-Line Testing Symposium (IOLTS), Corfu, Greece, pp. 206-207, 2010. POS
  90. Sobeeh Almukhaizim, Sara Bunian and Ozgur Sinanoglu, “Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints”, IEEE European Test Symposium (ETS), Prague, Czech Republic, pp. 248, 2010. POS
  91. Nader Al-Awadhi, Ozgur Sinanoglu and Mohammed Al-Mulla, “Add-On Techniques and Algorithms for Improving Stimulus Compression”, IEEE European Test Symposium (ETS), Prague, Czech Republic, pp. 245, 2010. POS
  92. Samah Saeed and Ozgur Sinanoglu, “Design and Analysis of an Adaptive X-Tolerant XOR Compactor with Controllable Fan-out”, IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, USA, 2010. PrOnly
  93. Nader Al-Awadhi, and Ozgur Sinanoglu, “Improving the Effectiveness of XOR-Based Decompressors Through Horizontal/Vertical Move of Stimulus Fragments”, IEEE International Symposium on Defect and Fault Tolerance (DFTS), Chicago, IL, USA, pp. 295-303, 2009.
  94. Ozgur Sinanoglu and Sobeeh Almukhaizim, “X-Alignment Techniques for Improving the Observability of Response Compactors”, IEEE International Test Conference (ITC), Austin, TX, USA, paper 17.1, 2009.
  95. Mohammed Taha, Nader Al-Awadhi, Ozgur Sinanoglu, and Mohammed Al-Mulla, “Align-Encode Delay Assignment In The Case of XOR-Decompressors: Impact of Parallel Computations”, WSEAS International Conference on Applied Computer and Applied Computational Science, Hangzhou, China, pp. 351-359, 2009.
  96. Ozgur Sinanoglu and Sobeeh Almukhaizim, “H-Align: Improving the Scan Cell Observability of Horizontal Response Compactors”, IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, USA, 2009. PrOnly
  97. Nader Al-Awadhi, Ozgur Sinanoglu and Mohammed Al-Mulla, “Align-Encode with XOR Decompressors”, IASTED International Symposium on Advances in Computer Science and Engineering, Phuket, Thailand, paper 646-075, 2009.
  98. Ozgur Sinanoglu, “Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors”, IEEE International Test Conference (ITC), Santa Clara, CA, USA, paper 35.2, 2008.
  99. Sobeeh Almukhaizim and Ozgur Sinanoglu, “Peak Power Reduction Through Dynamic Partitioning of Scan Chains”, IEEE International Test Conference (ITC), Santa Clara, CA, USA, paper 9.2, 2008.
  100. Ozgur Sinanoglu and Erik Jan Marinissen, “Analysis of Test Data Volume Reduction of Modular SOC Testing”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Munich, Germany, pp. 182-187, 2008.
  101. Sobeeh Almukhaizim and Ozgur Sinanoglu, “A Hazard-Free Majority Voter for TMR-Based Fault Tolerance in Asynchronous Circuits”, IEEE International Design and Test Workshop (D&T), pp. 93-98, 2007.
  102. Ozgur Sinanoglu and Tsvetomir Petrov, “A Non-Intrusive Isolation Approach for Soft Cores”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Nice, France, pp. 27-32, 2007.
  103. Ozgur Sinanoglu and Philip Schremmer, “Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations”, IEEE/ACM Design Automation Test in Europe Conference (DATE), Nice, France, pp. 516-521, 2007.
  104. Ozgur Sinanoglu and Alex Orailoglu, “Pipelined Test of SOC Cores Through Test Data Transformations”, IEEE European Test Symposium (ETS), Corsica, France, pp. 86-91, 2004
  105. Ozgur Sinanoglu and Alex Orailoglu, “Autonomous Yet Deterministic Test of SOC Cores For Minimal SOC Test Time”, IEEE International Test Conference (ITC), Charlotte, NC, USA, pp. 1359-1368, 2004.
  106. Ozgur Sinanoglu and Alex Orailoglu, “Scan Power Minimization Through Stimulus and Response Transformations”, IEEE/ACM Design Automation Test in Europe (DATE), Paris, France, pp. 404-409, 2004.
  107. Ozgur Sinanoglu and Alex Orailoglu, “Efficient RT-level Fault Diagnosis Methodology”, IEEE Asian South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, pp. 212-217, 2004.
  108. Baris Arslan, Ozgur Sinanoglu and Alex Orailoglu, “Extending the Applicability of Parallel-Serial Scan Design”, IEEE International Conference on Computer Design (ICCD), San Jose, CA, USA, pp. 200-203, 2004.
  109. Ozgur Sinanoglu and Alex Orailoglu, “Efficient RT-level Fault Diagnosis Methodology”, IEEE Workshop on RT-Level Testing (WRTLT), Xi’an, China, 2003.
  110. Ozgur Sinanoglu and Alex Orailoglu, “Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test”, IEEE Asian Test Symposium (ATS), Xi’an, China,, pp. 202-207, 2003.
  111. Ozgur Sinanoglu and Alex Orailoglu, “Aggressive Test Power Reduction Through Test Stimuli Transformation”, IEEE International Conference on Computer Design (ICCD), San Jose, CA, USA, pp. 542-547, 2003.
  112. Ozgur Sinanoglu and Alex Orailoglu, “Partial Core Encryption for Performance-Efficient Test of SOCs”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, pp. 910-94, 2003.
  113. Ozgur Sinanoglu and Alex Orailoglu, “Hierarchical Constraint Conscious RT-level Test Generation”, IEEE Euro-Micro Digital System Design (Euro-Micro DSD), Antalya, Turkey, pp. 312-318, 2003.
  114. Ozgur Sinanoglu and Alex Orailoglu, “Modeling Scan Chain Modifications for Scan-in Test Power Minimization”, IEEE International Test Conference (ITC), Charlotte, NC, USA, pp. 602-611, 2003.
  115. Ozgur Sinanoglu and Alex Orailoglu, “Parity-Based Output Compaction for Core-Based SOCs”, IEEE European Test Workshop (ETW), Maastricht, The Netherlands, pp. 15-20, 2003.
  116. Ozgur Sinanoglu and Alex Orailoglu, “A Novel Scan Architecture for Power-Efficient, Rapid Test”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, pp. 299-303, 2002.
  117. Ozgur Sinanoglu and Alex Orailoglu, “Fast and Energy-Frugal Deterministic Test Through Test Data Correlation Exploitation”, IEEE Defect and Fault Tolerance Symposium in VLSI Systems (DFTS), Vancouver, CA, pp 325-333, 2002.
  118. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, “Scan Power Reduction Through Test Data Transition Frequency Analysis”, IEEE International Test Conference (ITC), pp. 844-850, Baltimore, MD, USA, 2002.
  119. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, “Dynamic Test Data Transformations for Average and Peak Power Reductions”, IEEE European Test Workshop (ETW), pp. 113-118, Corfu, Greece, 2002.
  120. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, “Test Power Reduction Through Minimization of Scan Chain Transitions”, IEEE VLSI Test Symposium (VTS), Monterey, CA, USA, pp. 166-172, 2002.
  121. Ozgur Sinanoglu and Alex Orailoglu, “Compaction Schemes with Minimum Test Application Time”, IEEE Asian Test Symposium (ATS), Kyoto, Japan, pp. 199-204, 2001.
  122. Ozgur Sinanoglu and Alex Orailoglu, “Space and Time Compaction Schemes for Embedded Cores”, IEEE International Test Conference (ITC), Baltimore, MD, USA, pp. 521-529, 2001.
  123. Ozgur Sinanoglu and Alex Orailoglu, “Aliasing-free Space and Time Compaction for Embedded Cores”, IEEE Testing of Embedded Core-based Systems (TECS), Los Angeles, CA, USA, 2001. PrOnly
  124. Ozgur Sinanoglu and Alex Orailoglu, “Symbol Based Parallel RT-level Fault Simulation”, International Test Synthesis Workshop (ITSW), Santa Barbara, CA, USA, 2001. PrOnly
  125. Ozgur Sinanoglu and Alex Orailoglu, “RT-level Fault Simulation Based on Symbolic Propagation”, IEEE VLSI Test Symposium (VTS), Los Angeles, CA, USA, pp. 240-245, 2001.